Phys Start | End | Virtual Start2 | PCI Start1 | Contents |
0000.0000 | 01FF.FFFF | 0 and C0000000 | 0000.0000 | 32 meg SDRAM |
4000.0000 | 4000.FFFF | DRAM mode registers | ||
4100.0000 | 410F.FFFF | E18x.xxxx | 1 meg flash ROM | |
4200.0000 | 420F.FFFF | E10x.xxxx | CSR | |
5000.0000 | 5000.0FFF | E130.0xxx | StrongARM cache flush (no stalls) | |
7800.0000 | 7800.0FFF | E120.0xxx | PCI write flush | |
7900.0000 | 7900.0003 | E110.0000 | PCI IACK address | |
7B00.0000 | 7BFF.FFFF | E01x.xxxx | PCI config | |
7C00.0000 | 7C00.0FFF | E000.0xxx | PCI I/O space | |
8000.0000 | 80FF.FFFF | D0xx.xxxx | 08xx.xxxx | VGA |
9000.0000 | 9000.FFFF | D100.xxxx | modem codec | |
A000.0000 | A000.00FF | E140.00xx | 2000.00xx | Ethernet 100 |
Address | Name | Width | Meaning |
40000088 | DRAM_MODE_BK0 | w | Bank0 DRAM mode command register
(write) address bits set: 4 bit burst, interleave, latency=2 (read) forces a precharge; used to wake up DRAM at power up |
40004088 | DRAM_MODE_BK1 | w | Bank1 DRAM mode command register |
40008088 | DRAM_MODE_BK2 | w | Bank2 DRAM mode command register |
4000C088 | DRAM_MODE_BK3 | w | Bank3 DRAM mode command register |
Address | Name | Width | Meaning |
42000000 | FB_VENDID | s | vendor ID 0x1011 |
42000002 | FB_DEVID | s | device ID 0x1065 |
42000004 | FB_CSR_CMD | s | CSR command
1=enable FB as i/o target 2=enable FB as memory target 4=enable FB as PCI master 0x10=enable "write and invalidate" cycles 0x100=enable fast back-to-back PCI transactions |
42000006 | FB_CSR_STAT | s | CSR status
0x1000=target abort detected 0x2000=master abort detected 0x4000=system error detected (usually parity) 0x8000=parity error detected |
42000008 | FB_CSR_REV | w | rev and class code: 0x0b400100 |
4200000C | b | cache line size: set it to 8 | |
4200000D | b | latency timer: set it to 4 or 8 | |
42000010 | FB_CSR_MEM_BASE | w | CSR memory base address: set to 42000000 |
42000014 | FB_CSR_IO_BASE | w | CSR i/o base address: set to 42000000 |
42000018 | FB_CSR_DRAM_BASE | w | DRAM memory base address: set to 0 |
42000030 | FB_CSR_FLASH_BASE | w | flash ROM base address: set to 4100000 |
42000068 | FB_FLASH_WR_ADDR | b | flash write: lower 2 bits required to write the flash |
42000080-420000FF | FB_DMA_CONTROL | DMA control registers | |
42000100 | FB_DRAM_ADDR_MASK | w | DRAM address mask: set to 0x01FC0000 |
42000104 | FB_DRAM_ADDR_OFS | w | DRAM address offset: set to 0 |
42000108 | w | flash ROM address offset: set to 0 | |
4200010C | FB_DRAM_TIMING | w | DRAM timing: set to 01 (2 cycle precharge)
+ 4 (3 cycle write recovery) + 0x20 (2 cycle ras to cas) + 0x80 (2 cycle cas latency) + 0x400 (4 cycle after refresh) + 0x200000 (30x32 cycles between refreshes) |
42000110 | FB_DRAM_SIZE0 | w | DRAM bank 0 size register: set to 4 (for 8MB)
+ 0x10 (for 16Mb/chip) + 0 (for base) alternatives: 0x15 for 16MB 0x4E for 32MB |
42000114 | FB_DRAM_SIZE1 | w | DRAM bank 1 size register: set to 0x00800014 |
42000118 | FB_DRAM_SIZE2 | w | DRAM bank 2 size register: set to 0x01000014 |
4200011C | FB_DRAM_SIZE3 | w | DRAM bank 3 size register: set to 0x01800014 |
4200013C | FB_TIMING | w | SA-110 control:
1=set when PCI config is complete 2=set to assert SERR 8=read SERR 0x20=read PCI parity error 0x2000=enable timer 4 as watchdog 0xC000=set ROM as byte wide 0x40000=set ROM access time 0x400000=set ROM 2nd access time 0x1000000=setROM tristate time 0x80000000=reads state of pci_cfn (PCI central function) |
42000140 | w | PCI entension addresses: set to 0x7C007C00 | |
42000144 | FB_PREFETCH | w | PCI prefetch control
1=enable PCI prefetch 2=use "read multiple", 0=use "read line" 0xC=prefetch 8 words 0x0007FE00=prefetch 0x80000000 to BFFFFFFF only |
42000148 | w | arbiter priorities: set to 0x1F for all high
also: cycle times for X-bus and interrupt level selection !! |
bit | meaning | cleared by... |
0 | n/a | |
1 | soft interrupt | write 0 to IrqSoft/FiqSoft |
2 | console rx | |
3 | console tx | |
4 | timer 1 | Timer1Clear |
5 | timer 2 | Timer2Clear |
6 | timer 3 | Timer3Clear |
7 | timer 4 (watchdog) | Timer4Clear |
8 | IRQ0 (Ether10) | see Ether10 chip |
9 | IRQ1(Ether100) | see Ether100 chip |
10 | not available (used as timer input) | |
11 | IRQ3(Gint) | see IDE chip |
12-15 | n/a | |
16 | DMA1 | |
17 | DMA1 | |
18 | PCI_IRQ | |
19-21 | ||
22 | start BIST | write 0 to BIST bit 6 |
23 | received SERR | read control reg |
24-26 | n/a | |
27 | discard timer expired | read control reg |
28 | PCI data parity | read PCI status reg |
29 | PCI master abort | read PCI status reg |
30 | PCI target abort | read PCI status reg |
31 | PCI general parity | read PCI status reg |
Address | Name | Width | Meaning |
42000180 | FB_IRQ_STATUS | w | IrqStatus: (read only) 1 means the interrupt is enabled and active |
42000184 | FB_IRQ_RAW | w | IrqRawStatus: (read only) 1 means the interrupt is active |
42000188 | FB_IRQ_ENABLE | w | IrqEnable: (read only) 1 means the interrupt is enabled |
42000188 | FB_IRQ_SET | w | IrqEnableSet (write only): 1 means set enable |
4200018C | FB_IRQ_CLR | w | IrqEnableClear: (write only) 1 means clear the enable bit |
42000190 | FB_IRQ_SOFT | w | IrqSoft: (write only) sets the software interrupt (bit 1 only) |
42000280 | FB_FIQ_STAT | w | FiqStatus: (read only) 1 means the interrupt is enabled and active |
42000284 | FB_FIQ_RAW | w | FiqRawStatus: (read only) 1 means the interrupt is active |
42000288 | FB_FIQ_ENABLE | w | FiqEnable: (read only) 1 means the interrupt is enabled |
42000288 | FB_FIQ_SET | w | FiqEnableSet (write only): 1 means set enable |
4200028C | FB_FIQ_CLR | w | FiqEnableClear: (write only) 1 means clear the enable bit |
42000290 | FB_FIQ_SOFT | w | FiqSoft: (write only) sets the software interrupt (bit 1 only) |
Address | Name | Width | Meaning |
42000300 | FB_TIMER0_LOAD | w | Timer1Load: inital count |
42000304 | FB_TIMER0_VALUE | w | Timer1Value: current count |
42000308 | FB_TIMER0_CONTROL | w | Timer1Control: counter source, reload/wrap option, enable |
4200030C | FB_TIMER0_CLR | w | Timer1Clear: any write will clear |
Offset | Width | Meaning |
0 | s | Vendor ID |
2 | s | Device ID |
4 | s | command
1=I/O space enable 2=memory space enable 4=bus master enable 0x100=SERR enable 0x200=fast "back to back" enable |
6 | s | status
0x80=fast "back to back" capable 0x800=signalled target abort 0x1000=received target abort 0x2000=received master abort 0x4000=signalled SERR 0x8000=detected parity error |
8 | w | class & rev |
0xD | b | latency: each one is different |
0xE | b | header type |
0x10 | w | base address: set each one different |
Physical Address | Virtual Address | Width | Meaning |
7B08.0000 | E018.0000 | 256b | VGA config registers
set 7B08.0010 to 8000.0001 |
7B10.0000 | E020.0000 | 256b | Ether100 config registers
set 7B10.0014 to 90000000 set 7B10.0040 to Ether100 operating mode: 0x8000.0000=sleep mode, clocks off 0x4000.0000=snooze mode, low power, wakes up on net activity |
7B20.0000 | E030.0000 | 256b | VidComp config registers
assert(vendorID==0x1050 && deviceID==0x9960) set 7B20.0010 to A000.0000 (register access) set 7B20.0014 to A100.0000 (frame buffer) |
7B40.0000 | E050.0000 | 256b | IDE config registers
assert(vendor ID==0x10AD && deviceID==0x0565) set 7B40.0010 to B0000000 (not used) set 7B40.0110 to 8003.0001 (IDE data registers) |
7B80.0000 | E090.0000 | 256b | Ether10 config registers
assert(vendorID==0x1050 && deviceID==0x5A5A) set 7B80.0010 to 7C040001 (i/o space) |
Address | Name | Width | Meaning |
7B400040 | IDE_PCI_CONTROL | b | PCI control reg
1=PCI NMI enable 2=retry enable 4=posted write enabled (PCI to ISA) 0x20=enable interrup ack command |
7B400043 | IDE_IRQ_ROUTE | b | IDE interrupt routing control
default 0xEF: primary IDE irq is 14, secondary is 15 |
7B400044 | IDE_IRQ_ROUTE1 | s | PCI interrupt routing control
0-0xF: routing for INTD- pin 0x10-0xF0 routing for INTC- pin 0x100-0xF00 routing for INTB- pin 0x1000-0xF000 routing for INTA- pin |
7B400046 | IDE_BIOS_TIMER | s | BIOS timer base address: default 0x78
+1=timer enable |
7B40004C | IDE_CLOCK_DIV | b | clock divisor (PCI bus clock to BCLK)
5= divide by 8 8=reset drive |
7B400080 | IDE_ARBIT_PRIORITY | b | PCI arbiter priority control: TBD |
7B400081 | IDE_ARBIT_EXT_CONTROL | b | PCI arbiter priority ext control: TBD |
7B400082 | IDE_ARBIT_ENH_CONTROL | b | PCI arbiter priority enh control: TBD |
7B400083 | IDE_ARBIT_CONTROL | b | PCI arbiter control
1=lock enable, set to 1 2=CPU part, set to 2 4=arbiter timeout enable, set to 4 0x10=timeout after 8 clocks 0x80=guaranteed access timing, set it |
7B400140 | IDE_CONTROL | w | IDE control
1=primary port enable 2=port 0 fast mode (16 bit) 0x10=secondary port enable 0x20=port 1 fast mode (16 bit) set bit 11 (0x800) to 0 routesprimary IDE to irq14 and secondary to irq15 0xFF0000=read ahead 256 bytes |
7B400144,48,4C,50 | IDE_DRIVE_CONTROL0,1,2,3 | w[4] | IDE drive control registers, timing for disk access
set to 0x000002E2 for PIO Mode 3 set to 0x000002E0 for PIO Mode 4 |