| Address | Name | Width | Meaning |
| 4200.0000 | FB_VENDID | s | vendor ID 0x1011 |
| 4200.0002 | FB_DEVID | s | device ID 0x1065 |
| 4200.0004 | FB_CSR_CMD | s | CSR command
1=enable FB as i/o target 2=enable FB as memory target 4=enable FB as PCI master 0x10=enable "write and invalidate" cycles 0x100=enable fast back-to-back PCI transactions |
| 4200.0006 | FB_CSR_STAT | s | CSR status
0x1000=target abort detected 0x2000=master abort detected 0x4000=system error detected (usually parity) 0x8000=parity error detected |
| 4200.0008 | FB_CSR_REV | w | rev and class code: 0x0b400100 |
| 4200.000C | b | cache line size: set it to 8 | |
| 4200.000D | b | latency timer: set it to 4 or 8 | |
| 4200.0010 | FB_CSR_MEM_BASE | w | CSR memory base address: set to 4200.0000 |
| 4200.0014 | FB_CSR_IO_BASE | w | CSR i/o base address: set to 4200.0000 |
| 4200.0018 | FB_CSR_DRAM_BASE | w | DRAM memory base address: set to 0 |
| 4200.0030 | FB_CSR_FLASH_BASE | w | flash ROM base address: set to 4100000 |
| 4200.0068 | FB_FLASH_WR_ADDR | b | flash write: lower 2 bits required to write the flash |
| 4200.0080-4200.00FF | FB_DMA_CONTROL | DMA control registers | |
| 4200.0100 | FB_DRAM_ADDR_MASK | w | DRAM address mask: set to 0x01FC0000 |
| 4200.0104 | FB_DRAM_ADDR_OFS | w | DRAM address offset: set to 0 |
| 4200.0108 | w | flash ROM address offset: set to 0 | |
| 4200.010C | FB_DRAM_TIMING | w | DRAM timing: set to 01 (2 cycle precharge)
+ 4 (3 cycle write recovery) + 0x20 (2 cycle ras to cas) + 0x80 (2 cycle cas latency) + 0x400 (4 cycle after refresh) + 0x200000 (30x32 cycles between refreshes) |
| 4200.0110 | FB_DRAM_SIZE0 | w | DRAM bank 0 size register: set to 4 (for 8MB)
+ 0x10 (for 16Mb/chip) + 0 (for base) alternatives: 0x15 for 16MB 0x4E for 32MB |
| 4200.0114 | FB_DRAM_SIZE1 | w | DRAM bank 1 size register: set to 0x00800014 |
| 4200.0118 | FB_DRAM_SIZE2 | w | DRAM bank 2 size register: set to 0x01000014 |
| 4200.011C | FB_DRAM_SIZE3 | w | DRAM bank 3 size register: set to 0x01800014 |
| 4200.013C | FB_TIMING | w | SA-110 control:
1=set when PCI config is complete 2=set to assert SERR 8=read SERR 0x20=read PCI parity error 0x2000=enable timer 4 as watchdog 0xC000=set ROM as byte wide 0x40000=set ROM access time 0x400000=set ROM 2nd access time 0x1000000=setROM tristate time 0x80000000=reads state of pci_cfn (PCI central function) |
| 4200.0140 | w | PCI entension addresses: set to 0x7C007C00 | |
| 4200.0144 | FB_PREFETCH | w | PCI prefetch control
1=enable PCI prefetch 2=use "read multiple", 0=use "read line" 0xC=prefetch 8 words 0x0007FE00=prefetch 0x80000000 to BFFFFFFF only |
| 4200.0148 | w | arbiter priorities: set to 0x1F for all high
also: cycle times for X-bus and interrupt level selection !! |
| bit | meaning | cleared by... |
| 0 | n/a | |
| 1 | soft interrupt | write 0 to IrqSoft/FiqSoft |
| 2 | console rx | |
| 3 | console tx | |
| 4 | timer 1 | Timer1Clear |
| 5 | timer 2 | Timer2Clear |
| 6 | timer 3 | Timer3Clear |
| 7 | timer 4 (watchdog) | Timer4Clear |
| 8 | IRQ0 (Ether10) | see Ether10 chip |
| 9 | IRQ1(Ether100) | see Ether100 chip |
| 10 | not available (used as timer input) | |
| 11 | IRQ3(Gint) | see IDE chip |
| 12-15 | n/a | |
| 16 | DMA1 | |
| 17 | DMA1 | |
| 18 | PCI_IRQ | |
| 19-21 | ||
| 22 | start BIST | write 0 to BIST bit 6 |
| 23 | received SERR | read control reg |
| 24-26 | n/a | |
| 27 | discard timer expired | read control reg |
| 28 | PCI data parity | read PCI status reg |
| 29 | PCI master abort | read PCI status reg |
| 30 | PCI target abort | read PCI status reg |
| 31 | PCI general parity | read PCI status reg |
| Address | Name | Width | Meaning |
| 4200.0180 | FB_IRQ_STATUS | w | IrqStatus: (read only) 1 means the interrupt is enabled and active |
| 4200.0184 | FB_IRQ_RAW | w | IrqRawStatus: (read only) 1 means the interrupt is active |
| 4200.0188 | FB_IRQ_ENABLE | w | IrqEnable: (read only) 1 means the interrupt is enabled |
| 4200.0188 | FB_IRQ_SET | w | IrqEnableSet (write only): 1 means set enable |
| 4200.018C | FB_IRQ_CLR | w | IrqEnableClear: (write only) 1 means clear the enable bit |
| 4200.0190 | FB_IRQ_SOFT | w | IrqSoft: (write only) sets the software interrupt (bit 1 only) |
| 4200.0280 | FB_FIQ_STAT | w | FiqStatus: (read only) 1 means the interrupt is enabled and active |
| 4200.0284 | FB_FIQ_RAW | w | FiqRawStatus: (read only) 1 means the interrupt is active |
| 4200.0288 | FB_FIQ_ENABLE | w | FiqEnable: (read only) 1 means the interrupt is enabled |
| 4200.0288 | FB_FIQ_SET | w | FiqEnableSet (write only): 1 means set enable |
| 4200.028C | FB_FIQ_CLR | w | FiqEnableClear: (write only) 1 means clear the enable bit |
| 4200.0290 | FB_FIQ_SOFT | w | FiqSoft: (write only) sets the software interrupt (bit 1 only) |
| Address | Name | Width | Meaning |
| 4200.0300 | FB_TIMER0_LOAD | w | Timer1Load: inital count |
| 4200.0304 | FB_TIMER0_VALUE | w | Timer1Value: current count |
| 4200.0308 | FB_TIMER0_CONTROL | w | Timer1Control: counter source, reload/wrap option, enable |
| 4200.030C | FB_TIMER0_CLR | w | Timer1Clear: any write will clear |