| Offset | Width | Meaning |
| 0 | s | Vendor ID |
| 2 | s | Device ID |
| 4 | s | command
1=I/O space enable 2=memory space enable 4=bus master enable 0x100=SERR enable 0x200=fast "back to back" enable |
| 6 | s | status
0x80=fast "back to back" capable 0x800=signalled target abort 0x1000=received target abort 0x2000=received master abort 0x4000=signalled SERR 0x8000=detected parity error |
| 8 | w | class & rev |
| 0xD | b | latency: each one is different |
| 0xE | b | header type |
| 0x10 | w | base address: set each one different |
| Physical Address | Virtual Address | Width | Meaning |
| 7B08.0000 | E018.0000 | 256b | VGA config registers
set 7B08.0010 to 8000.0001 |
| 7B10.0000 | E020.0000 | 256b | Ether100 config registers
set 7B10.0014 to 90000000 set 7B10.0040 to Ether100 operating mode: 0x8000.0000=sleep mode, clocks off 0x4000.0000=snooze mode, low power, wakes up on net activity |
| 7B20.0000 | E030.0000 | 256b | VidComp config registers
assert(vendorID==0x1050 && deviceID==0x9960) set 7B20.0010 to A000.0000 (register access) set 7B20.0014 to A100.0000 (frame buffer) |
| 7B40.0000 | E050.0000 | 256b | IDE config registers
assert(vendor ID==0x10AD && deviceID==0x0565) set 7B40.0010 to B0000000 (not used) set 7B40.0110 to 8003.0001 (IDE data registers) |
| 7B80.0000 | E090.0000 | 256b | Ether10 config registers
assert(vendorID==0x1050 && deviceID==0x5A5A) set 7B80.0010 to 7C040001 (i/o space) |
| Address | Name | Width | Meaning |
| 7B40.0040 | IDE_PCI_CONTROL | b | PCI control reg
1=PCI NMI enable 2=retry enable 4=posted write enabled (PCI to ISA) 0x20=enable interrup ack command |
| 7B40.0043 | IDE_IRQ_ROUTE | b | IDE interrupt routing control
default 0xEF: primary IDE irq is 14, secondary is 15 |
| 7B40.0044 | IDE_IRQ_ROUTE1 | s | PCI interrupt routing control
0-0xF: routing for INTD- pin 0x10-0xF0 routing for INTC- pin 0x100-0xF00 routing for INTB- pin 0x1000-0xF000 routing for INTA- pin |
| 7B40.0046 | IDE_BIOS_TIMER | s | BIOS timer base address: default 0x78
+1=timer enable |
| 7B40.004C | IDE_CLOCK_DIV | b | clock divisor (PCI bus clock to BCLK)
5= divide by 8 8=reset drive |
| 7B40.0080 | IDE_ARBIT_PRIORITY | b | PCI arbiter priority control: TBD |
| 7B40.0081 | IDE_ARBIT_EXT_CONTROL | b | PCI arbiter priority ext control: TBD |
| 7B40.0082 | IDE_ARBIT_ENH_CONTROL | b | PCI arbiter priority enh control: TBD |
| 7B40.0083 | IDE_ARBIT_CONTROL | b | PCI arbiter control
1=lock enable, set to 1 2=CPU part, set to 2 4=arbiter timeout enable, set to 4 0x10=timeout after 8 clocks 0x80=guaranteed access timing, set it |
| 7B40.0140 | IDE_CONTROL | w | IDE control
1=primary port enable 2=port 0 fast mode (16 bit) 0x10=secondary port enable 0x20=port 1 fast mode (16 bit) set bit 11 (0x800) to 0 routesprimary IDE to irq14 and secondary to irq15 0xFF0000=read ahead 256 bytes |
| 7B40.0144,48,4C,50 | IDE_DRIVE_CONTROL0,1,2,3 | w[4] | IDE drive control registers, timing for disk access
set to 0x000002E2 for PIO Mode 3 set to 0x000002E0 for PIO Mode 4 |