Start Up Items
Flash access
At power up, all StrongARM reads will come from the FLASH ROM, until the
first StrongARM write occurs. This gives us a few cycles of execution where
the StrongARM fetches the reset vector code. This will appear to be location
0 of the FLASH. Fairly quickly, we should add 0x4100.0000 to the program
counter, so that instruction fetches are from the FLASH address space.
Then, issue a store instruction, which will change the memory
map to the final one.
Memory
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configure DRAM controller
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set up address mux size, timing, refresh, etc (0x4200.00xx)
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test the RAM size
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test the RAM
Devices
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set up the '553 PCI arbiter
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set up the FB PCI port
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poll the PCI devices and assert VendorID && DeviceID (0x7B00.00xx)
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set the PCI device addresses (0x7B00.00xx)
Interrupts
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set up the FB interrupt controller
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set up the '553 interrupt controller
DMA
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disable FB DMA manager
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set up '553 DMA manager
Memory Manager
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turn on ICache
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set memory pages; logical addresses will be determined by the OS
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turn on DCache
Serial Port (Console)
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by now, the PCI port to the SuperIO chip should be running
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set SuperIO PnP ports: 7C03.13F0, ports write CR07, assert CR20, CR21,
write CR60, CR61, CRF0
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select 24MHz clock
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set UART ports: (0x7C03.120x), write UCR, HSR, baud rate (24MHz/115K/16=13!)